• Medientyp: E-Artikel
  • Titel: Implementing the scale vector-thread processor
  • Beteiligte: Krashinsky, Ronny; Batten, Christopher; Asanović, Krste
  • Erschienen: Association for Computing Machinery (ACM), 2008
  • Erschienen in: ACM Transactions on Design Automation of Electronic Systems
  • Sprache: Englisch
  • DOI: 10.1145/1367045.1367050
  • ISSN: 1084-4309; 1557-7309
  • Schlagwörter: Electrical and Electronic Engineering ; Computer Graphics and Computer-Aided Design ; Computer Science Applications
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  • Beschreibung: <jats:p> The Scale vector-thread processor is a complexity-effective solution for embedded computing which flexibly supports both vector and highly multithreaded processing. The 7.1-million transistor chip has 16 decoupled execution clusters, vector load and store units, and a nonblocking 32KB cache. An automated and iterative design and verification flow enabled a performance-, power-, and area-efficient implementation with two person-years of development effort. Scale has a core area of 16.6 mm <jats:sup>2</jats:sup> in 180 nm technology, and it consumes 400 mW--1.1 W while running at 260 MHz. </jats:p>